The present invention relates to computer memory systems, and more specifically, to per-die based memory refresh control based on a master controller.
The phrase “memory wall problem” is used to refer to the growing disparity of speed between contemporary computer processors and computer memory located outside of the computer processors. Hybrid memory cube (HMC) technology targets the memory wall problem by stacking several dynamic random access memory (DRAM) dies over a logic die. In a HMC, memory modules are placed as stacked integrated circuits (or dies) in cubes, as opposed to being placed flat next to each other on a motherboard. In contemporary implementations of HMC, the number of stacked memory dies can be either four or eight, and all of the dies (memory and logic) are interconnected using Through Silicon Vias (TSVs). HMCs generally provide higher bandwidth, and consume less energy and area when compared to the conventional double data rate (DDR) memory modules.
Within a HMC, the memory is divided into multiple vaults. Each vault is completely independent in that it conducts its functions and operations independently of the other vaults. Each vault contains its own memory controller that manages all of the memory operations with the vault by adhering to the timing constraints. Refresh operations for memory locations within the vault are issued by the memory controller in the vault.